Nitride semiconductor devices have characteristics such as exhibiting high saturated electron velocity and a wide band gap. Such characteristics have been utilized to advance development of devices having a high withstand voltage and high power. Examples of the nitride semiconductor devices used for development of such devices having a high withstand voltage and high power include field-effect transistors, in particular, high electron mobility transistors (HEMTs).
An example of HEMTs is a GaN-HEMT (AlGaN/GaN-HEMT) having an HEMT structure in which an AlGaN electron supply layer is disposed on a GaN electron transit layer. In the GaN-HEMT, strain is generated in AlGaN owing to difference in a lattice constant between AlGaN and GaN, and the strain causes piezoelectric polarization. This piezoelectric polarization and the spontaneous polarization of the AlGaN cause high-concentration two dimensional electron gas (2DEG) to be generated. Hence, the GaN-HEMT enables development of devices having a high withstand voltage and high power.
In the GaN-HEMT, however, high-concentration 2DEG makes operation in a normally-off mode difficult. In a technique for enabling operation in a normally-off mode, for example, part of an electron supply layer right below a gate electrode is etched to interrupt the flow of 2DEG. This technique is herein referred to as a first technique. Furthermore, in another technique for enabling operation in a normally-off mode, for instance, a p-type GaN layer is formed right below a gate electrode to counteract 2DEG. This technique is herein referred to as a second technique. Such a structure is also referred to as a p-GaN gate structure. Furthermore, for example, in a technique for enabling operation in a normally-off mode as well as enabling both a low source resistance and operation at a high operating voltage, a 2DEG-reducing layer doped with a p-type dopant and a low-resistance layer doped with an n-type dopant are formed so as to overlie part of an electron supply layer between a source electrode and a gate electrode. This technique is herein referred to as a third technique. Moreover, for example, in a technique for enabling operation in a normally-off mode as well as enabling both a low on-resistance and a high withstand voltage, part of an electron transit layer underlying a source electrode and a gate electrode is doped with a p-type dopant. This technique is herein referred to as a fourth technique.
In the first technique, however, the etching damages part of a normally-off transistor below the gate electrode, which causes increases in on-resistance and a leak current. Hence, the first technique is impractical for enabling steady operation in a normally-off mode with a low on-resistance. In the second technique, the counteraction of 2DEG by the p-type GaN layer for operation in a normally-off mode entails a reduction in the thickness of the electron supply layer; however, in this case, it is difficult to enable a low on-resistance and a high withstand voltage. In particular, in the case where the thickness of the electron supply layer is reduced for enabling operation in a normally-off mode, the distance between the gate electrode and the drain electrode is increased to achieve a high withstand voltage; however, the increase in the distance therebetween results in an increase in on-resistance. Thus, the second technique is unsuitable for enabling operation in a normally-off mode as well as enabling a low on-resistance and a high withstand voltage.
In the third technique, since the p-type dopant added to the 2DEG-reducing layer is diffused to the electron supply layer or the electron transit layer during the crystal growth thereof. Thus, the third technique is impractical for enabling operation in a normally-off mode as well as enabling a low on-resistance and a high withstand voltage. In the third technique, for instance, even though the thickness of the electron supply layer and the distance between the gate electrode and the drain electrode are increased to achieve a high withstand voltage as well as a low on-resistance, such an approach does not work well to keep the on-resistance in a low level. In addition, since the third technique involves a structure in which the 2DEG-reducing layer and the low-resistance layer are merely laminated, the electron mobility is low, and the channel resistance is high; hence, the on-resistance is not successfully reduced.
In the fourth technique, the p-type dopant added to part of the electron transit layer is diffused to the other part of the electron transit layer during the crystal growth thereof. Thus, the fourth technique is impractical for enabling operation in a normally-off mode as well as enabling a low on-resistance and a high withstand voltage. In the fourth technique, for example, even though the thickness of the electron supply layer and the distance between the gate electrode and the drain electrode are increased to achieve a high withstand voltage as well as a low on-resistance, such an approach does not work well to keep the on-resistance in a low level.
The followings are reference documents:    [Document 1] Japanese Laid-open Patent Publication No. 2009-76845,    [Document 2] Japanese Laid-open Patent Publication No. 2007-19309,    [Document 3] International Publication Pamphlet No. WO 2010/016564, and    [Document 4] Japanese Laid-open Patent Publication No. 2004-260140.